RISC-V CPU

Advanced RISC-V CPU with Tomasulo Architecture

RISC-V CPU: Advanced CPU Design with Tomasulo Architecture

Complete Independent Implementation GitHub Repository

A sophisticated RISC-V CPU implementation featuring Tomasulo’s algorithm for out-of-order execution, designed and implemented from scratch with FPGA deployment capabilities.

Advanced Features

  • Tomasulo Architecture: Full out-of-order execution with dynamic instruction scheduling
  • RV32IC Instruction Set: Complete implementation of 37 base instructions plus compressed extensions
  • Instruction Cache: Optimized instruction fetching and caching mechanisms
  • Memory Management: Efficient load/store operations with hazard detection
  • FPGA Deployment: Successfully synthesized and deployed on physical FPGA hardware

My Complete Implementation

Architecture Design: Designed complete Tomasulo-based CPU architecture from scratch, implementing dynamic instruction scheduling and register renaming

Instruction Set Implementation: Built comprehensive RV32IC support including 37 base instructions and 25 compressed instruction variants

Out-of-Order Execution: Implemented full Tomasulo algorithm with reservation stations, register renaming, and dynamic scheduling

Memory System: Developed efficient memory interface with load/store buffers and hazard detection mechanisms

FPGA Integration: Successfully synthesized design for FPGA deployment with complete test suite validation

Performance Optimization: Achieved efficient instruction throughput through advanced pipeline design and cache optimization

Technical Achievements

Complete RV32IC Support: Implemented all required instructions including arithmetic, logical, control flow, and memory operations

Tomasulo Algorithm: Full implementation of out-of-order execution with reservation stations and register renaming

Instruction Cache: Designed and implemented instruction caching system for improved performance

FPGA Deployment: Successfully synthesized and deployed on physical FPGA hardware with comprehensive testing

Test Suite Validation: Passed all simulation and FPGA tests with complete instruction set coverage

Built entirely independently to explore advanced CPU architecture concepts, demonstrating deep understanding of modern processor design principles through practical implementation.

RISC-V CPU architecture showing Tomasulo pipeline, instruction cache, and out-of-order execution components.
FPGA deployment results and performance benchmarks showcasing the CPU's efficient execution and successful hardware implementation.