cv

My academic and professional experience

Basics

Name Weixian Xu
Label AI Researcher
Email hz.czar@sjtu.edu.cn
Url https://HZxCzar.github.io
Summary Researcher working on self-improving AI and human-centered intelligence: systems that learn from analysis and reflection, improve over time, and help people in meaningful ways. I am an undergraduate in the ACM Honors Class at Shanghai Jiao Tong University and currently conduct research at Stanford SALT Lab with Prof. Diyi Yang.

Work

  • 2026.06 - Present
    Student Researcher
    Stanford SALT Lab
    Research on human-centered self-improving AI with Prof. Diyi Yang.
    • Studying how recursive self-improvement can be directed toward broader, human-centered intelligence.
    • Exploring AI systems that learn from analysis and reflection, then help people in meaningful ways.
  • 2025.12 - 2026.06
    Research Collaborator
    Princeton / AI2 Collaboration
    Collaborated with Prof. Mengdi Wang and Shilong Liu on EEVEE.
    • Developed a multi-dataset test-time prompt learning framework for self-improving agents.
    • Studied router-prompt co-evolution under heterogeneous real-world task streams.
  • 2025.06 - 2026.06
    Research Intern
    GAIR Lab, Shanghai Jiao Tong University
    Research on self-improving AI systems and autonomous discovery with Prof. Pengfei Liu.
    • First author of ASI-Evolve, a closed-loop framework for self-improving AI research.
    • Core contributor to ASI-Arch (1.1k+ GitHub stars).
    • Designed autonomous pipelines executing 1,773 experiments.
    • Contributed to state-of-the-art architecture discovery.

Volunteer

  • 2025.09 - Present
    Class Monitor
    ACM Honors Class
    Led the ACM cohort, coordinating schedules and managing administrative tasks.
  • 2025.03 - 2025.06
    Head Teaching Assistant
    Shanghai Jiao Tong University
    Data Structures (CS1951), lectured by Prof. Yong Yu.
  • 2024.09 - 2025.01
    Teaching Assistant
    Shanghai Jiao Tong University
    Programming (CS1953), lectured by Prof. Huiyu Weng.

Education

  • 2023.09 - 2027.06

    Shanghai, China

    Bachelor of Science
    Shanghai Jiao Tong University
    Computer Science (ACM Honors Class)
    • Large Language Models (A+)
    • Compiler Design (A+)
    • Computer Systems (A+)
    • Advanced Compiler Design (A+)

Awards

Publications

Skills

Research Focus
Recursive Self-Improvement
Self-Improving Agents
Test-Time Learning
Human-Centered AI
Engineering & Systems
Rust
C++
Verilog
Operating System Kernels
Compiler Design
Hardware Architecture
Tools & Frameworks
PyTorch
Transformers
CUDA
Linux
Docker
Git
LaTeX

Languages

Chinese
Native speaker
English
Fluent (TOEFL: 104, Speaking: 25)

Interests

Continual Self-Improvement
Recursive Self-Improvement
Long-Horizon Learning
Reflection and Adaptation
Self-Improving Research Agents
Human-Centered Intelligence
Human-AI Collaboration
Social Benefit
Useful Intelligence

Projects

  • 2025.05 - 2026.04
    ASI-Evolve
    Agentic framework for recursive self-improvement in AI research.
    • Learn-design-experiment-analyze loop
    • Cognition base and dedicated analyzer
    • Discovery across data, architectures, and learning algorithms
  • 2025.12 - 2026.06
    EEVEE
    Multi-dataset test-time prompt learning for self-improving agents.
    • Router-prompt co-evolution
    • Heterogeneous task streams
    • Reduced cross-dataset interference
  • 2025.06 - 2025.09
    ASI-Arch
    Autonomous AI system for neural architecture discovery (1.1k+ GitHub stars).
    • 1.1k+ GitHub stars
    • 1,773 autonomous experiments
    • State-of-the-art architectures discovered
  • 2025.04 - 2025.06
    ACore
    Comprehensive operating system kernel implementation in Rust.
    • Virtual Memory & Page Allocation
    • Process Scheduling & Threads
    • VFS & Multiple Filesystems
    • User/Kernel Isolation
  • 2025.04 - 2025.06
    Imxc
    High-performance compiler for a C-like language.
    • Performance comparable to Clang
    • Mem2Reg & Graph Coloring RegAlloc
    • Function Inlining & SCCP
    • Incremental Compilation
  • 2024.09 - 2025.01
    RISC-V CPU
    Verilog implementation of RISC-V core with Tomasulo architecture.
    • Tomasulo Algorithm (Out-of-Order)
    • RV32IC Instruction Set
    • FPGA Deployment Capable
    • Instruction Cache