Weixian Xu
ACM Honors Class, Shanghai Jiao Tong University
Weixian Xu
Third-year Undergraduate
ACM Honors Class
Shanghai Jiao Tong University
GAIR Lab
About Me
I am Weixian Xu, a third-year undergraduate at the ACM Honors Class, Shanghai Jiao Tong University. Currently, I am a research intern at GAIR Lab, supervised by Prof. Pengfei Liu.
My research philosophy is grounded in the belief that AI should evolve from static tools into dynamic partners. While I possess a strong background in systems programming (OS & Compilers) and Neural Architecture Search, my current focus is on building systems capable of interactive evolution—learning and adapting continuously through long-term human interaction.
Research Focus
My research pursues the vision of Self-Evolving AI. I identify the critical limitations in current models as the lack of sustained self-improvement and long-horizon reliability.
To address this, my work proceeds on two fronts:
- Internal Architecture: Refining the learning objectives and memory mechanisms of individual models to enable continuous growth.
- System Strategy: Engineering multi-agent ecosystems where models collaborate and optimize via complex interaction protocols.
Ultimately, I aim to empower human-centric models that utilize affective understanding to deeply align with user preferences over time.
Current Projects
ASI-Arch: Autonomous Neural Architecture Discovery
Research Project (GAIR Lab) | Paper | Code (1.1k Stars)
An autonomous AI system designed to conduct neural architecture discovery and reveal new design patterns without human intervention.
- Impact: The repository garnered 1.1k+ stars within a month of publication.
- Contribution: Designed the autonomous discovery pipeline, orchestrated 1,773 large-scale experiments, and validated 105 state-of-the-art architectures.
ACore: Operating System Kernel
System Implementation | Code
A comprehensive OS kernel exploring core operating system concepts through independent development in Rust.
- Implemented memory management with virtual memory and page allocation.
- Developed process scheduling, thread management, and a VFS layer supporting multiple filesystems.
- Engineered user/kernel space isolation for security.
Imxc: Advanced Compiler
System Implementation | Code
A full-featured compiler for a C-like language (Mx*), achieving performance comparable to Clang.
- Implemented advanced optimizations including Mem2Reg, Function Inlining, SCCP, and ADCE.
- Designed a high-performance Register Allocation module using Graph Coloring.
- Supported incremental compilation for efficient multi-file builds.
RISC-V CPU (Tomasulo Architecture)
Hardware Implementation | Code
A sophisticated RISC-V processor core implementation in Verilog.
- Features Tomasulo architecture for dynamic instruction scheduling and out-of-order execution.
- Supports the complete RV32I instruction set with FPGA deployment capabilities.
Technical Background
- Research: Python, PyTorch, Transformers, CUDA, Continual Learning, Neural Architecture Search.
- Systems: Rust, C++, C, Verilog, OS Development, Compiler Design.
- Infrastructure: Linux, Docker, Git, CI/CD.
Personal Interests
Beyond research and coding, music is a big part of my life. I play both acoustic and electric guitar, and I hold a Grade 9 certification in Clarinet. I also enjoy playing badminton to stay active and exploring video games for their storytelling and mechanics. Back in high school, I was a competitive physics student (CPhO Provincial Second Prize), which shaped my analytical thinking.
On a more personal note, I am happily in a relationship and value the time spent exploring life’s journey with my partner.
Contact
I am always open to discussing AI evolution, memory mechanisms, systems engineering, or potential collaborations.
- Email: hz.czar@sjtu.edu.cn
- GitHub: @HZxCzar